Reduced Area Discrete-Time Down-Sampling Filter Embedded With Windowed Integration Samplers

摘要

Developing a flexible receiver, which can be reconfigured to multiple standards,is the key to solving the problem of embedding numerous and ever-changingfunctionalities in mobile handsets. Difficulty in efficiently reconfiguring analog blocksof a receiver chain to multiple standards calls for moving the ADC as close to theantenna as possible so that most of the processing is done in DSP. Different standardsare sampled at different frequencies and a programmable anti-aliasing filtering is neededhere. Windowed integration samplers have an inherent sinc filtering which creates nullsat multiples of fs. The attenuation provided by sinc filtering for a bandwidth B is directlyproportional to the sampling frequency fs and, in order to meet the anti-aliasingspecifications, a high sampling rate is needed. ADCs operating at such a highoversampling rate dissipate power for no good use. Hence, there is a need to develop aprogrammable discrete-time down-sampling circuit with high inherent anti-aliasingcapabilities. Currently existing topologies use large numbers of switches and capacitorswhich occupy a lot of area.A novel technique in reducing die area on a discrete-time sinc2 ?2 filter forcharge sampling is proposed. An SNR comparison of the conventional and the proposedtopology reveals that the new technique saves 25 percent die area occupied by the samplingcapacitors of the filter. The proposed idea is also extended to implement higher downsamplingfactors and a greater percentage of area is saved as the down-sampling factor isincreased. The proposed filter also has the topological advantage over previouslyreported works of allowing the designers to use active integration to charge thecapacitance, which is critical in obtaining high linearity.A novel technique to implement a discrete-time sinc3 ?2 filter for windowedintegration samplers is also proposed. The topology reduces the idle time of theintegration capacitors at the expense of a small complexity overhead in the clockgeneration, thereby saving 33 percent of the die area on the capacitors compared to thecurrently existing topology.Circuit Level simulations in 45 nm CMOS technlogy show a good agreementwith the predicted behaviour obtained from the analaysis.